Low Power Bit-Parallel Cellular Multiplier Implemetation in Secure Dual-Rail Adiabatic Logic
نویسندگان
چکیده
منابع مشابه
Ultra Low Power Symmetric Pass Gate Adiabatic Logic with CNTFET for Secure IoT Applications
With the advent and development of the Internet of Things, new needs arose and more attention was paid to these needs. These needs include: low power consumption, low area consumption, low supply voltage, higher security and so on. Many solutions have been proposed to improve each one of these needs. In this paper, we try to reduce the power consumption and enhance the security by using SPGAL, ...
متن کاملLow-Power 4×4-Bit Array Two-Phase Clocked Adiabatic Static CMOS Logic Multiplier
The present study evaluates four designs of XOR using our previously reported two-phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. 2PASCL XOR, which demonstrates the lowest power dissipation, is used for a 4ˆ4-bit array 2PASCL multiplier. Based on simulation results obtained using 0.18 —m standard CMOS technology, at transition frequencies of 1 to 100 MHz, the 4ˆ4-bit arra...
متن کاملDesign of Low Power 4-bit ALU Using Adiabatic Logic
This paper presents the implementation of a 4-bit Arithmetic Logic Unit (ALU) using Complementary Energy Path Adiabatic Logic (CEPAL). This static adiabatic logic has proved its advantage through the minimization of the 1/2CVdd2 energy dissipation occurring every cycle. Firstly, the performance characteristics of CEPAL 4-to-1 multiplexer and full adder are compared against the conventional stat...
متن کاملLSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier
Keywords: Low-power Adiabatic logic Energy recovery Multiplier a b s t r a c t As the density and operating speed of complementary metal oxide semiconductor (CMOS) circuits increases, dynamic power dissipation has become a critical concern in the design and development—of personal information systems and large computers. The reduction of supply voltage, node capacitance, and switching activity ...
متن کاملPower Aware & High Speed Booth Multiplier based on Adiabatic Logic
Multiplier is one of the major arithmetic operations carried out in DSP applications. This paper presents a modified Booth multiplier based on adiabatic logic. It is composed of Booth encoder, multiplier containing partial product generators and 1-bit (half and full) adders and final adder. Booth multiplication allows for smaller, faster multiplication circuits through encoding the signed numbe...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: International Journal of Modeling and Optimization
سال: 2013
ISSN: 2010-3697
DOI: 10.7763/ijmo.2013.v3.292